In this tutorial, NVIDIA engineers and academic and industrial researchers will present CUDA and discuss its advanced use for science and engineering. The tutorial will demonstrate CUDA with traditional HPC examples including BLAS, FFT, and integration with Fortran and high-level languages (MATLAB, Mathematica, Python) and describe in detail the programming model at the heart of it all. It will then turn to advanced topics including optimizing CUDA programs, CUDA floating point performance and accuracy, and CUDA programming strategies and tips. Finally the tutorial will present detailed case studies in which domain scientists will describe their experience using CUDA to accelerate mature, deployed, real-world science codes. Scientists throughout industry and academia are already using CUDA to achieve dramatic speedups on production and research codes (see http://www.nvidia.com/cuda for a list of codes, academic papers and commercial packages based on CUDA). Presenters include Massimiliano Fatica (NVIDIA), Mark Harris (NVIDIA), Patrick LeGresley (NVIDIA), and Jim Phillips (UIUC). Follow this link to register.

In addition to the papers already announced, Dr. Simon Harding (Memorial University, Newfoundland) and Dr. Tien-Tsin Wong (The Chinese University of Hong Kong) will lead a discussion on the practicalities of running evolution on modern graphics cards. They will contrast the current leading GPGPU tools considering ease of use, and support for debugging and performance monitoring. CIGPU will close with a short session considering the future of computational intelligence on GPUs.

University of Waterloo
Waterloo, Ontario, Canada
May 27th 2008

This one-day symposium will explore the use of GPUs, CELL processors, FPGAs and multi-core CPUs for large-scale scientific computing. The symposium program includes invited talks on the LANL Roadrunner CELL supercomputer, the RapidMind platform for multicore CPUs and many-core accelerators, and NVIDIA CUDA. For more information, see http://www.sharcnet.ca/events/ssgc2008/

Slides from the 2007 AstroGPU conference, held at the Institute for Advanced Study in Princeton last November, have been posted to the AstroGPU Website.

In conjunction with The 2008 International Conference on Computational Science and Its Applications (ICCSA 2008, UCHPC '08 is a technical session on UnConventional High Performance Computing. This session focuses on uses of hardware for HPC that was not originally intended for HPC. UCHPC invites papers on all aspects of unconventional HPC and its related areas describing either proven and tested solutions or novel ideas and concepts. Topics for submissions include but are not limited to the following areas: cluster solutions; performance issues and scalability; innovative use of hardware and software; and HPC on GPUs, Cell BE, FPGAs and other hardware. Please see the Call for Papers for more information.

ARCS 2008, the 21st Conference on Architecture of Computing Systems, is proud to announce a full day GPGPU tutorial, covering concepts, building blocks and case studies with a special focus on NVIDIA CUDA GPU Computing technology. ARCS is held in Dresden, Germany, on February 25-28, 2008. For more details, please visit The ARCS 2008 Website.

novel scientific and engineering applications of GPUs. Papers submitted for special sessions will be peer-reviewed with the same criteria used for the contributed papers. Submission deadline is 7 January 2008. (WCCI-2008 Special Session Computational Intelligence on Consumer Games and Graphics Hardware CIGPU-2008)

The Workshop on General Purpose Processing on Graphics Processing Units will be held October 4, 2007 at Northeastern University, Boston, MA. This meeting will include a keynote talk by Prof. Wen-mei Hwu on "GP Computing: Hardware, Architecture Tools and Education". The program will include three invited talks from NVIDA ATI and IBM Research, and will include demos by GPU hardware and software vendors. The technical program will include 12 refereed papers. Registration is free, though you need to register for GPGPU at: http://censsis-db3.ece.neu.edu/RICC2007/regist.aspx Commercial companies that are interested in presenting at GPGPU, please contact the organizing committee at gpgpu@ece.neu.edu.

On Sunday November 11 2007 at SC07 in Reno NVIDIA will host a full-day tutorial on CUDA. In this tutorial NVIDIA engineers will partner with academic and industrial researchers to present CUDA and discuss its advanced use for science and engineering domains. The morning session will introduce CUDA programming and the execution and memory models at its heart, motivate the use of CUDA with many brief examples from different HPC domains, and discuss fundamental algorithmic building blocks in CUDA. The afternoon will discuss advanced issues such as optimization and "tips & tricks", and include real-world case studies from domain scientists using CUDA (VMD and NAMD Molecular Dynamics and Oil and Gas). Follow this link for more information: http://sc07.supercomputing.org/schedule/event_detail.php?evid=11034.

Northeastern University
Boston, MA USA
October 4, 2007

Overview: The goal of this workshop is to provide a forum for general-purpose purpose GPU programming environments and platforms, as well as discuss applications that have been able to harness the horsepower provided by these platforms. This year's workshop is particularly interested in imaging applications. Papers are being sought on many aspects of GPUs, including (but not limited to):

+ GPU applications
+ GPU software and operating systems
+ GPU programming environments
+ GPU power/efficiency
+ GPU architectures
+ GPU benchmarking/measurements

Paper Submission: Authors should submit an 8 page paper in IEEE double-column style to gpgpu@ece.neu.edu.

Industry Participation: The workshop encourages participation by GPU manufacturers, software vendors, or companies which develop or market products used by the GPU community. Any company interested in participating in the workshop should contact the workshop organizer at gpgpu@ece.neu.edu.

Important Dates:
Paper submission: August 28, 2007
Author notification: September 7, 2007
Final paper: September 14, 2007

Copies of final papers will be made available at the workshop. In addition, selected papers will be invited to be part of a special issue of an ACM or IEEE journal or magazine. For more information, see the GPGPU 2007 web page

On 4-5 August 2007, San Diego hosted the annual Graphics Hardware conference. GPGPU figured prominently in three papers:

- As transistors get smaller, their transient failure rates increase. Future architectures must adapt to address the resulting reliability problems. Jeremy Sheaffer presented a paper demonstrating a hardware-based redundancy approach to ensure reliability on GPGPU applications. ("A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors". Jeremy Sheaffer, University of Virginia; David Luebke, NVIDIA Research; Kevin Skadron, University of Virginia.)

- Magnus Strengert presented a generic, minimally intrusive, and application-transparent GLSL debugger that operates transparently to the application. In it, shader debugging is performed on a per-draw call level; it allows singlestepping and the inspection of arbitrary variable content. Linux code is available and Windows code is expected by the end of the year. ("A Hardware-Aware Debugger for the OpenGL Shading Language". Magnus Strengert, Thomas Klein, and Thomas Ertl, University of Stuttgart.)

- One critical need for GPGPU developers is a library of general-purpose building blocks for GPU computation. Shubhabrata Sengupta presented a paper describing a GPU implementation of the "scan primitives" and their use in novel GPU implementations of quicksort, efficient sparse matrix-vector multiplication, and tridiagonal matrix systems. This paper won the Best Paper award and the authors are preparing an open-source release. ("Scan Primitives for GPU Computing". Shubhabrata Sengupta, UC Davis; Mark Harris, NVIDIA Corporation; Yao Zhang, UC Davis; John D. Owens, UC Davis.)

All Graphics Hardware 2007 papers are available in the ACM digital library. In addition, the GH07 program page contains slides for all talks as well as two keynote talks (Chas. Boyd of the Microsoft DirectX team: "Mass Market Applications of Data-Parallel Computing" and Michael Jones, chief technologist of Google Earth: "GPUs for the true mass market") and vendor talks from AMD and NVIDIA about their latest processors (AMD Radeon HD 2900 and NVIDIA's Tesla).

A new workshop called AstroGPU 2007: General Purpose Computation on GPUs in Astronomy and Astrophysics will be held November 9-10th, 2007 at the Institute for Advanced Study in Princeton, NJ. The goal of this workshop is to explore and discuss the applicability of GPUs to astrophysical problems. It will bring together astrophysicists, colleagues from other areas of science where GPGPU techniques have been successfully applied, and representatives from the industry who will demonstrate in tutorial sessions the GPU hardware, programming tools, and GPGPU techniques. This workshop is geared towards astrophysicists wishing to learn GPGPU (specifically, CUDA) techniques and port their code to GPUs. For more information, see http://www.astrogpu.org.

I3D 2008 (aka the Symposium on Interactive 3D Graphics and Games) will be happening the weekend before GDC this year, February 15-17, in nearby Redwood City, CA. The Call For Participation is now up at the website: October 22 is this year's paper deadline. This is a small conference, 100 attendees or so, that offers a good opportunity to meet other people working on GPU related techniques. I3D 2007 included a number of GPGPU-related papers on interactive ray tracing, mesh simplification, and histogram generation; see Ke-Sen Huang's summary page. (CFP I3D 2008 page)

The trend of multicore processors development brings a shift of paradigm in applications development. Traditionally, increasing clock frequency is one of the main dimensions for conventional processors to achieve higher performance gains. Application developers used to improve performance of their applications by just waiting for faster processor platforms. Today, increasing clock frequency has reached a point of diminishing returns—and even negative returns if power is taken into account. Multicore processors, also known as Chip multiprocessors (CMPs), promise a power-efficiency way to increase performance and become more prevalent in vendors' solutions, for example, IBM CELL Broadband Engine processors, Intel Core 2 Dual processors, and so on. However, the application or algorithm development process must be significantly changed in order to fully explore the potential of multicore processors. This special issue of the Journal of VLSI Signal Processing Systems is to discuss related challenges, issues, case studies, and solutions, especially focusing on multimedia-related applications, architectures, and programming environments, for example, understanding the complexity of developing a new application or porting an existing application onto a multicore processor. (Call for papers)

Data-parallel programming models are emerging as an extremely attractive model for parallel programming, driven by several factors. Through deterministic semantics and constrained synchronization mechanisms, they provide race-free parallel-programming semantics. Furthermore, data-parallel programming models free programmers from reasoning about the details of the underlying hardware and software mechanisms for achieving parallel execution and facilitate effective compilation. Finally, efforts in the GPGPU movement and elsewhere have matured implementation technologies for streaming and data-parallel programming models to the point where high performance can be reliably achieved. This workshop gathers commercial and academic researchers, vendors, and users of data-parallel programming platforms to discuss implementation experience for a broad range of many-core architectures and to speculate on future programming-model directions. Participating institutions include AMD, Electronic Arts, Intel, Microsoft, NVIDIA, PeakStream, RapidMind, and The University of New South Wales. ( Link to Call for Participation, Data-Parallel Programming Models for Many-Core Architectures)

The proceedings of the workshop "General-Purpose GPU Computing: Practice And Experience" held at SuperComputing 2006 are now posted. The proceedings include PDFs of the workshop presentations and posters. http://www.gpgpu.org/sc2006/workshop/

Please join us next week in Tampa, Florida at Supercomputing 2006 for a full-day GPGPU Tutorial on Sunday, November 12 2006. This is the continuation of a series of well-regarded courses presented at the SIGGRAPH and IEEE Visualization conferences. The course at SC06 has been updated for the Supercomputing audience with the latest results and techniques. Then, on Monday November 13, plan to attend the SC06 Workshop, "General-Purpose GPU Computing: Practice and Experience". This workshop features invited speakers and poster presenters who provide insights into current GPGPU practice and experience, and chart future directions in heterogeneous and homogeneous multi-core processor architectures and data-parallel processor architectures such as GPUs.

SC'06 is proud to announce the "General-Purpose GPU Computing: Practice and Experience" workshop. This workshop features invited speakers and poster presenters who provide insights into current GPGPU practice and experience, and chart future directions in heterogeneous and homogeneous multi-core processor architectures and data-parallel processor architectures such as GPUs. The topics addressed by the speakers range from current GPGPU practice and experience to future issues and research areas in parallel computing currently being driven by GPGPU innovations and lessons learned, such as the IBM Cell Broadband Engine and Sun Microsystem's Niagara/Sun4v processor. Poster presentations are solicited in, but not strictly limited to, the following areas:

• Application acceleration
• GPGPU/multi-core/parallel coprocessor integration: toolkits, implementation techniques (e.g., iterative refinement, numerical techniques), domain-specific languages
• GPGPU implementation issues: performance issues and challenges, cooperative GPU/CPU algorithms and solutions, numerical analysis issues, HPC issues
• Cluster-based GPGPU computing and Grid integration

Please submit prospective poster abstracts in PDF or PostScript format to the workshop chair for consideration and review. Poster abstract submission deadline: No later than October 1st. (For more information see http://www.gpgpu.org/sc2006/workshop/)

• Location: Boston Convention and Exhibition Center
• Room: Room 108
• Date: Thursday, August 3rd
• Time: 11am-1:00pm

Since there is not a GPGPU course offering at SIGGRAPH this year, we have scheduled a GPGPU "Birds of a Feather" (BOF) for everyone interested in GPGPU at SIGGRAPH. The current plan is for the BOF to be an informal gathering to chat about GPGPU. Many of the academics doing research in GPGPU plan to be there, as well as industry folks, including ATI and Nvidia. Since the BOF is scheduled during lunch, it will be a "brown bag" event, so bring lunch with you. We'll keep you updated on any status changes in the forums. (Credit goes to Mike Houston for organizing.)

Abstracts, citations and links to author homepages of eight papers on GPGPU presented at the ICCS conference, Reading, UK, May 2006, are available. Topics include genome sequencing, GPGPU languages, database operations, computational fluid dynamics, computer vision, computational geometry and neural networks. (http://www.mathematik.uni-dortmund.de/~goeddeke/iccs/papers.html)